搜索资源列表
FIFO
- 一个异步的FIFO的VERILOG程序,有测试程序
FIFO
- fifo.v verilog实现的先进先出存储器
异步FIFO的VERILOG实现(格雷码)
- 使用格雷码实现异步FIFO
IDT FIFO 控制代码
- IDT FIFO的Verilog控制读写代码
实用verilog代码(乘法器,触发器,FIFO等)
- 本文件包含一些实用verilog程序代码,包括乘法器,除法器,伽罗瓦域乘法器,CORDIC数字计算机的设计,异步FIFO设计,伪随机序列应用设计,RS(204,188)译码器的设计,都是可综合的。对研究这部分的朋友有一定的帮助。
CY7C68013读写FIFO源代码
- CY7C68013读写FIFO源代码(Verilog),已测试
Verilog_CY7C68013-SLAVE-FIFO
- 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ,已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
FIFO
- 基于FPGA的FIFO控制器的设计与实现,ISE,verilog-FPGA-based design and implementation of FIFO controller, ISE, verilog
asfifodesign
- 异步fifo设计文档,里面包括详细的verilog设计方案及代码。fifo设计是通信中必然设计的设计-a fifo design with code inside, using verilog language
fifolifo
- fifo filo verilog 程序!先入先出数据存储器的程序和先入后出程序!-fifo filo verilog program! First in first out data memory of the program!
fifo
- 基于verilog的异步fifo设计,仿真效果良好-asynchronous fifo based on zhe verilog language
ad_da_ctr
- 基于FPGA的ad和da转换Verilog代码,FPGA采用ep2c5芯片,做成异步fifo,ad芯片采用TI的ths1230,da芯片采用TI的TLV5619,仿真结果基本正确。-FPGA-based ad and da conversion Verilog code, FPGA using ep2c5 chip, made ??of asynchronous fifo, ad-chip using TI s ths1230, da chip uses TI s TLV5619, simula
sdh
- SDH是现代光纤通信中广泛应用的数据传输格式,在SDH帧结构中,前9列为开销字节,它包含了很多重要的信息,本程序为SDH开销的接收处理,查找帧头,分频,勤务话字节E1异步fifo。可拆为三段源代码,不知道能不能抵三个程序-SDH is a modern optical fiber communication is widely used in data transmission format, in the SDH frame structure, as the former 9 overhea
USB_Interface
- verilog USB USB的slave fifo的控制-verilog USB
ref-sdr-sdram-verilog
- SDRAM的vegilog代码,做一个SDRAM的封装成为SRAM一样进行操作。一个顶层文件下由三个模块-SDRAM
VGA-VerilogHDL
- 用Verilog HDL编写的VGA显示驱动程序-Verilog HDL prepared with VGA display driver
FIFO1
- FIFO存储电路的设计与实现,用verilog实现fifo的参考设计-FIFO memory circuit design and realization of the realization of fifo with Verilog reference design
fifo
- 先入先出缓冲存储器,采用verilog hdl-FIFO buffer memory, using verilog hdl
fifo
- 可综合的Verilog FIFO存储器. This example describes a synthesizable implementation of a FIFO. -Can be integrated Verilog FIFO memory. This example describes a synthesizable implementation of a FIFO.
fifo
- 先进先出缓存器的verilog设计与实现-design of fifo(first in first out)